Abstract

In the last years, the SysML standard is attracting more attention from hardware designers. As UML, SysML has been used to automatically generate an HDL code written in SystemC, Verilog and VHDL. Contrarily to most existing works, we propose in this paper, a new reverse engineering approach to generate SysML definition bloc and internal bloc diagrams from VHDL code. Code generation is done on the basis of a set of well defined mapping rules between SysML and VHDL concepts. The benefit of our work is to enable both hardware and software designers to maintain and comprehend VHDL programs.

Information

Item Type:	Conference
Divisions:	» Symposium on Complex Systems and Intelligent Computing (CompSIC)
ePrint ID:	414
Date Deposited:	2015-09-19
Further Information:	Google Scholar
URI:	https://www.univ-soukahras.dz/en/publication/article/414

BibTex