Résumé

Every day, electromagnetic radio spectrums
become precious and expensive. Cognitive radios represent one of
the best solutions to improve the available radio frequency (RF)
spectrum utilization. Since many forms of communication do not
utilize the allocated spectrum fully. So, dynamic detection of no
utilized spectrum is crucial. Generally, energy sensing and
cyclostationary feature sensing are the most used techniques.
Traditional cyclostationary feature-sensing signal correlations
are implemented by a complex adder and complex multiplier,
which requires significant memory space to store filter
coefficients and increased hardware usage. To overcome the
above-mentioned problems, a complex pipelined multiply and
adder architecture is designed to reduce the area occupancy
further. In this research, complex multiplication is designed using
two absolute multipliers. The proposed architecture is coded
using VHDL on a Virtex-5 Field-Programmable Gate Array
(FPGA) device, and the results are compared with similar works.
The implementation demonstrates that the proposed operator
can reduce FPGA logic requirements with a high maximum
working frequency.

Information

Item Type:	Conference
Divisions:	» Laboratoire de Recherche en Électromécanique et Sûreté de Fonctionnement » Faculté des Sciences et de la Technologie
ePrint ID:	4724
Date Deposited:	2023-12-16
Further Information:	Google Scholar
URI:	https://www.univ-soukahras.dz/fr/publication/article/4724

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